There is an ever-present desire in the semiconductor fabrication industry to achieve individual devices with smaller physical dimensions. Reducing the dimensions of devices is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be placed on a given area of semiconductor material and the process yield and to reduce the unit cost and the power consumption of individual devices. In addition, scaling can result in performance increases of the individual devices as the charge carriers, having a finite velocity, have a shorter distance to travel and less bulk material has to accumulate or dissipate charges. Thus, the trend in the industry is towards thinner device regions and gate oxides, shorter channels, and lower power consumption.
However, scaling often creates some performance drawbacks. In particular, a known category of performance limitations known as short channel effects arises as the length of the channel of CMOS devices is reduced by scaling. One particular short-channel effect in CMOS devices, known as Drain Induced Barrier Lowering (DIBL), is significantly responsible for the degradation of sub-threshold swing in deep submicron devices. DIBL is a reduction in the potential barrier between the drain and source as the channel length shortens. When the drain voltage is increased, the depletion region around the drain increases and the drain region electric field reduces the channel potential barrier which results in an increased off-state or leakage current between the source and drain. This can cause increased power consumption, which is an issue of particular importance in portable, battery powered devices.
A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, the PFET pulling the output high and the NFET pulling the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (Vt) with respect to its source, the NFET is off, i.e., an open switch. Above Vt, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its Vt, i.e., less negative, and on below Vt. Hence, for a particular integrated circuit design, so called “short channel” parameters such as Vt, DIBL, and Ioff are important factors to consider. Therefore, it is desirable to have a semiconductor device with improved ability to specify short channel parameters.